Transistors having high electron mobility, for example HEMTs, are manufactured by epitaxial deposition of heterostructures such as AlGaN/GaN onto substrates made of sapphire, silicon carbide, and/or silicon. They are notable for a high charge carrier density in the channel region.
Conventionally, the gate electrode in HEMT transistors encompasses a Schottky contact, i.e., a metal-semiconductor transition. It is disadvantageous in this context that very high leakage currents occur at high voltages in the reverse state, and the component's losses are very high. It is furthermore disadvantageous that the maximum gate voltage is limited because the Schottky contact exhibits a very high leakage current as positive gate voltages become higher. The dynamic performance of the component is thereby impaired, and this can result in degradation and/or destruction of the component.
The maximum gate voltage can be raised by the fact that an insulating layer is disposed between the semiconductor layer (for example AlGaN) and the gate electrode so that a metal-insulated semiconductor contact is produced, with the result that the gate electrode of the HEMT transistor is insulated from the semiconductor layer. It is disadvantageous in this context, however, that both the interface from the semiconductor layer to the insulating layer and the interface from the insulating layer to the gate electrode, as well as the quality of the dielectric layer, are subject to stringent technological demands in terms of the dynamic performance and degradation of the component.
Two conventional methods, among others, are available for manufacturing an MIS gate transistor. In the first method, the ohmic contacts are manufactured earlier in time than the gate module, which has a gate dielectric and a gate electrode. Firstly ohmic contacts are generated, either before deposition of a passivating layer or after deposition of the passivating layer, by opening the passivating layer at the source and drain regions. This is followed by opening of the passivation at the gate region and optional deposition of gate dielectric, and obligatory deposition of gate metal. The gate electrode is then patterned, and further passivating and metallizing layers are generated.
It is disadvantageous in this context that metal-containing process steps are carried out before the gate module is manufactured, so that the gate dielectric in particular can become contaminated with metal, with the result that the performance of the transistor is considerably diminished.
In the second method, the ohmic contacts are generated later in time than the application of the gate dielectric. For this, a passivating layer is opened at the gate region and a gate dielectric is introduced into the opened region. The passivating layer is then opened at the source and drain regions, and the ohmic contacts are generated there. The gate electrode and further passivating and metallizing layers are then generated. Deposition of the gate dielectric thus occurs in metal-free sites.
It is nevertheless disadvantageous that the gate module can only be completed after manufacture of the ohmic contacts, and that because of a high temperature budget upon annealing of the ohmic contacts, the gate module exhibits interface degradation at the metal-dielectric surface.
An object of the present invention is to manufacture a robust gate contact.